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| SPT9691 WIDE INPUT VOLTAGE, JFET COMPARATOR FEATURES * * * * * * Common Mode Range -4.0 to +8.0 V Low Input Bias Current <100 pA Propagation Delay 2.5 ns (max) Low Offset 25 mV Low Feedthrough and Crosstalk Differential Latch Control APPLICATIONS * * * * * * * * Automated Test Equipment High-Speed Instrumentation Window Comparators High-Speed Timing Line Receivers High-Speed Triggers Threshold Detection Peak Detection GENERAL DESCRIPTION The SPT9691 is a high-speed, wide common mode voltage, JFET input, dual comparator. It is designed for applications that measure critical timing parameters in which wide common mode input voltages of -4.0 to +8.0 V are required. Propagation delays are constant for overdrives greater than 200 mV. JFET inputs reduce the input bias currents to the nanoamp level, eliminating the need for input drivers and buffers in most applications. The device has differential analog inputs and complementary logic outputs compatible with ECL systems. Each comparator has a complementary latch enable control that can be driven by standard ECL logic. The SPT9691 is available in 20-lead PLCC, 20-lead plastic DIP and 20-contact LCC packages over the commercial temperature range. It is also available in die form. BLOCK DIAGRAM QA QA GNDA LEA LEA DVEE(A) AVEE(A) AVCC(A) -INA +INA A B QB QB GNDB LE B LE B DV EE(B) AV EE (B) AVCC (B) -IN B +IN B Signal Processing Technologies, Inc. 4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25C Supply Voltages (Measured to GND) Positive Supply Voltage (AVCC) .............. -0.5 to +11.0 V Negative Supply Voltage (AVEE) ............ -11.0 to +0.5 V Negative Supply Voltage (DVEE) .............. -6.0 to +0.5 V Input Voltages Input Common Mode Voltage ........ DVEE-1 to +AVCC+1 Differential Input Voltage ...................... -12.0 to +12.0 V Input Voltage, Latch Controls .................. DVEE to 0.5 V VIN to AVCC Differential Voltage ................ -16 to +1.0 V VIN to AVEE Differential Voltage ................ +4 to +21.0 V Note: Output Output Current ....................................................... 30 mA Temperature Operating Temperature, ambient .................. 0 to +70 C junction ....................... +150 C Lead Temperature, (soldering 60 seconds) ........ +300 C Storage Temperature ................................ -65 to +150 C 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. Application of multiple maximum rating conditions at the same time may damage the device. ELECTRICAL SPECIFICATIONS T A = +25 C, AVCC = +10 V, AVEE=-10.0 V, DVEE=-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified. PARAMETERS DC ELECTRICAL CHARACTERISTICS Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias Current Input Offset Current Input Offset Current Positive Supply Current (Dual) Negative Supply Current (Dual) Negative Supply Current (Dual) Positive Supply Voltage, AVCC Negative Supply Voltage, AVEE Negative Supply Voltage, DVEE Input Common Mode Range Latch Enable Common Mode Range Differential Voltage Range Open Loop Gain Differential Input Resistance Input Capacitance TEST CONDITIONS TEST LEVEL MIN TYP MAX UNITS VIN,CM=0 TMIN < TA -25 -25 0.0 0.0 50 0.1 2.0 1.0 10 25 15 55 +25 +25 10 100 mV mV V/C nA nA nA nA mA mA mA V V V V V V dB G pF pF pF dB dB dB TMIN 33 20 70 10.25 -10.25 -5.45 +8.0 0 10 10.0 -10.0 -5.2 60 2 1.0 1.0 2.9 LCC Package PLCC Package PDIP Power Supply Sensitivity Common Mode Rejection Ratio TMIN < TA 50 45 60 60 55 SPT SPT9691 2 10/6/97 ELECTRICAL SPECIFICATIONS T A = +25 C, AVCC = +10 V, AVEE=-10.0 V, DVEE=-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified. PARAMETERS DC ELECTRICAL CHARACTERISTICS Power Dissipation Output High Level Output Low Level AC ELECTRICAL CHARACTERISTICS Propagation Delay1 Propagation Delay TEMPCO Propagation Delay Skew (A vs B) Propagation Delay Dispersion2 Latch Set-up Time Latch to Output Delay Latch Pulse Width Latch Hold Time Rise Time Fall Time Slew Rate TEST CONDITIONS TEST LEVEL MIN TYP MAX UNITS Dual ECL 50 Ohms to -2V ECL 50 Ohms to -2V I I I -.98 -1.95 700 895 -.70 -1.65 mW V V 150 mV O.D. IV V V 1.5 2.0 2 100 200 1.7 0.8 2 -1.9 0.4 0.4 3 2.5 ns ps/ C ps ps ns ns ns ns ns ns V/ns 150 mV Overdrive Min. V V 150 mV O.D. V V V 20% to 80% 20% to 80% V V V NOTES: 1 Valid for both high-to-low and low-to-high transitions. 2 Dispersion is the change in propagation delay due to changes in slew rate, overdrive, and common mode level. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 C. Parameter is guaranteed over specified temperature range. SPT SPT9691 3 10/6/97 TIMING INFORMATION The timing diagram for the comparator is shown in figure 1. If LE is high and LE low in the SPT9691, the comparator tracks the input difference voltage. When LE is driven low and LE high, the comparator outputs are latched into their existing logic states. The leading edge of the input signal (which consists of a 150 mV overdrive voltage) changes the comparator output after a time of tpdL or tpdH (Q or Q ). The input signal must be maintained for a time ts (set-up time) before the LE falling edge and LE rising edge and held for time tH after the falling edge for the comparator to accept data. After tH , the output ignores the input status until the latch is strobed again. A minimum latch pulse width of tpL is needed for strobe operation, and the output transitions occur after a time of tpLOH or tpLOL. Figure 1 - Timing Diagram Latch Enable 50% Latch Enable tH tS Differential Input Voltage VOD Output Q tpdL t pLOH 50% VRef VOS tpL 50% Output Q tpdH VIN +=300 mV, V =150 mV tpLOL OD The set-up and hold times are a measure of the time required for an input signal to propagate through the first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected and held; those occurring after tH will not be detected. Changes between tS and tH may not be detected. SWITCHING TERMS (Refer to figure 1) tpdH INPUT TO OUTPUT HIGH DELAY - The propagation delay measured from the time the input signal crosses the reference voltage ( the input offset voltage) to the 50% point of an output LOW to HIGH transition. tpdL INPUT TO OUTPUT LOW DELAY - The propagation delay measured from the time the input signal crosses the reference voltage ( the input offset voltage) to the 50% point of an output HIGH to LOW transition. tH MINIMUM HOLD TIME - The minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs. MINIMUM LATCH ENABLE PULSE WIDTH - The minimum time that the Latch Enable signal must be HIGH in order to acquire an input signal change. MINIMUM SET-UP TIME - The minimum time before the negative transition of the Latch Enable signal that an input signal change must be present in order to be acquired and held at the outputs. tpL tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to 50% point of an output LOW to HIGH transition. tpLOL LATCH ENABLE TO OUTPUT LOW DELAY - The propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to the 50% point of an output HIGH to LOW transition. tS VOD VOLTAGE OVERDRIVE - The difference between the differential input and reference input voltages. SPT SPT9691 4 10/6/97 TYPICAL PERFORMANCE CURVES INPUT OFFSET VOLTAGE VS COMMON MODE VOLTAGE (T=+25 C) +10.0 100 INPUT BIAS CURRENT VS COMMON MODE VOLTAGE (+25 C) +6.0 10 INPUT OFFSET VOLTAGE (mV) +2.0 INPUT BIAS CURRENT (nA) -4.0 -1.6 +0.8 +3.2 +5.6 +8.0 1.0 -2.0 0.1 -6.0 0.01 -10.0 0.001 -4.0 -1.6 +0.8 +3.2 +5.6 +8.0 COMMON MODE VOLTAGE (V) COMMON MODE VOLTAGE (V) PROPOGATION DELAY TIME VS TEMPERATURE (V OD=150 mV) 2.4 3.0 PROPAGATION DELAY TIME VS OVERDRIVE (mV) PROPAGATION DELAY TIME (ns) 2.8 2.2 PROPAGATION DELAY TIME (ns) 2.6 2.0 2.4 2.2 1.8 2.0 1.6 1.8 1.4 0 50 100 150 200 250 300 350 0 +25 +50 +75 +100 TEMPERATURE (C) OVERDRIVE (mV) RISE AND FALL OF OUTPUTS VS TIME CROSSOVER -.90 HYSTERESIS VS LATCH 20 -1.10 15 OUTPUT RISE AND FALL (V) -1.30 HYSTERESIS (mV) VIN (CM) = 0.0 V 10 -1.50 5 -1.70 -1.90 1.1 1.5 1.9 2.3 2.7 3.5 0 -20 0 20 40 60 TIME (ns) LATCH = (VLE - VLE) mV SPT SPT9691 5 10/6/97 GENERAL INFORMATION The SPT9691 is an ultrahigh-speed dual voltage comparator. It offers tight absolute characteristics. The device has differential analog inputs and complementary logic outputs compatible with ECL systems. The output stage is adequate for driving terminated 50 ohm transmission lines. The SPT9691 has a complementary latch enable control for each comparator. Both should be driven by standard ECL logic levels. A common mode voltage range of -4 V to +8 V is achieved by a proprietary JFET input design which requires a separate negative power supply (AVEE). The dual comparators have separate AVCC, AVEE, DVEE, and grounds for each comparator to achieve high crosstalk rejection. Single channel operation can be accomplished by floating all pins (including the ground and supply pins) of the unused comparator. Power dissipation during single channel operation is 50% of the dissipation during dual channel operation. Figure 2 - Internal Function Diagram Q +IN + - PRE AMP LATCH ECL OUT - IN Q REF 1 REF 2 CLK BUF AV EE DV EE VCC GND LE LE SPT SPT9691 6 10/6/97 TYPICAL INTERFACE CIRCUIT The typical interface circuit using the comparator is shown in figure 3. Although it needs few external components and is easy to apply, there are several conditions that should be noted to achieve optimal performance. The very high operating speeds of the comparator require careful layout, decoupling of supplies, and proper design of transmission lines. Since the SPT9691 comparator is a very high frequency and high gain device, certain layout rules must be followed to avoid oscillations. The comparator should be soldered to the board with component lead lengths kept as short as possible. A ground plane should be used, while the input impedance to the part is kept as low as possible, to decrease parasitic feedback. If the output board traces are longer than approximately half an inch, microstripline techniques must be employed to prevent ringing on the output waveform. Also, the microstriplines must be terminated at the far end with the characteristic impedance of the line to prevent reflections. All supply voltage pins should be decoupled with high frequency capacitors as close to the device as possible. All ground pins should be connected to the same ground plane to further improve noise immunity and shielding. If using the SPT9691 as a single comparator, the outputs of the inactive comparator can be grounded, left open or terminated with 50 Ohms to -2 V. All outputs on the active comparator, whether used or unused, should have identical terminations to minimize ground current switching transients. Diode D1 connected between AVCC and GND is recommended to prevent possible damage to the device in case the AVCC supply is disconnected. The diode should be a 1N914 or equivalent. If AVCC is disconnected with this diode in place, there will be approximately a 6 mA current draw from both AVEE and DVEE. Diode D2 connected between AVEE and DVEE is necessary to avoid power supply sequence latch-up. This diode keeps AVEE (also the substrate) less than a silicon diode drop away from the most negative circuit potential if DVEE is powered up first. This diode should be a 1N5817 (Schottky) or equivalent. Note: At no time should both inputs be allowed to float with power applied to the device. At least one of the inputs should be tied to a voltage within the common mode range (-4.0 to +8.0 V) to prevent possible damage to the device. To prevent possible latch-up during initial power up, the input voltages should not exceed 1 V. Additional protection diodes D3-D6 should be used on the inputs if there is the possibility of exceeding the absolute maximum ratings of the inputs with respect to AVCC and DVEE (1N914 or equivalent). NOTE: For ease of implementation, all diodes (D1 - D6) can be 1N5817 (Schottky) or equivalent. Figure 3 - SPT9691 Typical Interface Circuit Figure 4 - SPT9691 Typical Interface Circuit With Hysteresis AVCC AVEE DVEE AVCC D1 .1 F D3 D6 .1 F D2 D1 .1 F .1 F AVEE D2 .1 F .1 F D3 D6 D4 D5 D4 D5 VIN VREF Noninverting Input + LE LE RL 50 ECL -2 V RL 50 Q Output Q Output VIN VREF Noninverting Input + LE RL 50 -1.3 V 100 .1 F -2 V DVEE GND GND Q Output Q Output Inverting Input LE Inverting Input RL 50 .1 F .1 F -2 V AVEE DVEE AVCC GND = Represents line termination. AVEE DVEE AVCC GND = Represents line termination. SPT SPT9691 7 10/6/97 PACKAGE OUTLINES 20-Lead Plastic DIP INCHES MIN MAX 0.014 0.300 0.026 .100 typ .010 typ 1.20 typ 0.330 0.254 1.030 MILLIMETERS MIN MAX 0.36 7.62 0.66 2.54 0.25 30.48 8.38 6.45 26.16 SYMBOL A B C 20 G 1 D E F G H 0.290 0.246 1.010 7.37 6.25 25.65 H F E A D B C 20-Lead Plastic Leaded Chip Carrier (PLCC) A B Pin 1 G SYMBOL N INCHES MIN MAX .045 typ 0.350 0.385 0.350 0.385 0.042 0.165 0.085 0.025 0.015 0.026 0.013 0.290 0.356 0.395 0.356 0.395 0.056 0.180 0.110 0.040 0.025 0.032 0.021 0.050 0.330 MILLIMETERS MIN MAX 1.14 8.89 9.78 8.89 9.78 1.07 4.19 2.16 0.64 0.38 0.66 0.33 7.37 9.04 10.03 9.04 10.03 1.42 4.57 2.79 1.02 0.64 0.81 0.53 1.27 8.38 A B C D E F G H I J K L M N O TOP VIEW F E MO L C D K J I H Pin 1 BOTTOM VIEW SPT SPT9691 8 10/6/97 PACKAGE OUTLINES 20-Contact Leadless Chip Carrier (LCC) A H G SYMBOL A B C D E F G H INCHES MIN MAX .040 typ .050 typ 0.055 0.360 0.066 .020 typ 0.028 0.075 MILLIMETERS MIN MAX 1.02 1.27 1.40 9.14 1.68 0.51 0.71 1.91 B Bottom View Pin 1 0.045 0.345 0.054 0.022 1.14 8.76 1.37 0.56 C D F E SPT SPT9691 9 10/6/97 PIN ASSIGNMENTS QA 1 QA 2 GNDA 3 LEA 4 LEA 5 DIP/PDIP DVEE(A) 6 AVEE(A) 7 AVCC(A) 8 -INA 9 +INA 10 15 DV EE(B) 14 AV EE(B) 13 AVCC (B) 12 -IN B 11 +IN B 20 QB 19 QB 18 GNDB 17 LE B PIN FUNCTIONS NAME QA QA GNDA LE A LEA AVCC(A) AVEE(A) DVEE(A) AVCC(B) AVEE(B) DVEE(B) -INA +INA +INB -INB 18 LEB 17 LEB TOP VIEW FUNCTION Output A Inverted Output A Ground A Inverted Latch Enable A Latch Enable A Positive Supply Voltage (+10 V) Negative Supply Voltage (-10 V) Negative Supply Voltage (-5.2 V) Positive Supply Voltage (+10 V) Negative Supply Voltage (-10 V) Negative Supply Voltage (-5.2 V) Inverting Input A Noninverting Input A Noninverting Input B Inverting Input B Inverted Latch Enabled B Latch Enable B Ground B Inverted Output B Output B 16 LE B QA 3 GNDA LEA LEA 4 5 6 QA 2 QB 1 QB GNDB 20 19 LE B LEB GNDB QB QB LCC/PLCC 16 DVEE(B) 15 AVEE(B) 14 AVCC(B) DVEE(A) 7 AVEE(A) 8 9 10 11 12 13 AVCC(A) -INA +INA +INB -INB ORDERING INFORMATION PART NUMBER SPT9691SCC SPT9691SCN SPT9691SCP SPT9691SCU TEMPERATURE RANGE 0 to +70 C 0 to +70 C 0 to +70 C +25 C PACKAGE TYPE 20C LCC 20L Plastic DIP 20L Plastic Leaded Chip Carrier (PLCC) Die* *Please see the die specification for guaranteed electrical performance. Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty. SPT SPT9691 10 10/6/97 |
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